The present invention relates to the field of programmable logic devices, and particularly programmable logic devices which implement high speed synchronous state machines.
Typical prior art programmable logic devices (PLD) (which are sometimes also referred to as programmable logic arrays) have been used for asynchronour programmable logic. Examples of such programmable logic devices are well known in the art and are shown, for example, in U.S. Pat. Nos. 4,124,899; 4,609,986 and 4,617,479. The operation of these devices typically involves applying inputs to the input terms (typically shown as the vertical lines on a diagram illustrating the array), which input terms control the outputs of the various product terms (typically shown as the horizontal lines depicted in diagrams of the array). In a typical implementation of a programmable logic array using MOS (metal-oxide-semiconductor) field effect transistors, such as EPROMs (electrically programmable read only memory), a transistor or plurality of transistors is located at each intersection of a product term and input term in the array. Programming of a PLD proceeds in the well known manner as described in the prior art, such as the patents described above; also see an application assigned to the instant assignee filed Dec. 8, 1987, having Ser. No. 07/129,990.
Initial implementations of programmable logic devices often utilized registers, such as D flip-flops, at the outputs of the device. In these implementations, these registers were typically provided solely for outputting information from the array while there were inputs for the PLD which were dedicated solely to inputting information. Subsequent designs have included I/O pads (pins or connector means) which may be used for inputting or outputting because the pads are connected to programmable output cells which permit the pad to be used as an output or as an input. The user of these subsequent designs also has the option of not using the pad for inputting and feeding back the internal output from the array back to the array. The feedback to the array and the input from the I/O (input/output) pad is multiplexed through an input/feedback multiplexer (MUX). These programmabale outputs are now referred to programmable macrocells and do allow the user to control whether a pin is utilized for inputting or outputting. An example of these programmable macrocells are found incommercially available IC chips referred to as the 22V10.
These prior art designs often penalize users who wish to use the programmable logic array as a high speed synchronous state machine because a particular macrocell can not simultaneously allow inputting and outputting. Moreover, information available sooner than the next rising edge (or falling edge if so designed) of the state clock can not be input to the PLD but rather must wait until the next rising edge (or falling edge) of the state clock. These drawbacks make difficult the use of PLD's for high speed synchronous state machines. The present invention provides an architecture for a PLD, and particularly an architecture for a macrocell, such as a dual macrocell (having two I/O pads (connector means)) which permit the use of the PLD architecture as a high speed synchronous state machine.